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ZY1207 7A No-Bus POL Data Sheet
3V to 14V Input ? 0.5V to 5.5V Output
6.
Typical Application
IBV
ENABLE
CS
TRIM
VREF
EN
ENP
SYNC
OK
PGOOD
TEMP
VLDO
VIN
VIN
VIN
VIN
VIN
CS
TRIM
VREF
EN
ENP
SYNC
OK
PGOOD
TEMP
VLDO
VIN
VIN
VIN
VIN
VIN
CCA2
CCA2
CCA1
POL2
22uF 4.7uF 4.7uF
CCA1
POL4
22uF 4.7uF 4.7uF
CCA0
CCA0
INTL4
INTL3
INTL2
+VS
VOUT
VOUT
VOUT
VOUT
VOUT
INTL4
INTL3
INTL2
+VS
VOUT
VOUT
VOUT
VOUT
VOUT
Vo2
IM
DELAY
PGND
PGND
PGND
PGND
PGND
PGND
PGND
220uF
47uF
47uF
IM
DELAY
PGND
PGND
PGND
PGND
PGND
PGND
PGND
220uF
47uF
47uF
CS
TRIM
VREF
EN
ENP
SYNC
OK
PGOOD
TEMP
VLDO
VIN
VIN
VIN
VIN
VIN
CS
TRIM
VREF
EN
ENP
SYNC
OK
PGOOD
TEMP
VLDO
VIN
VIN
VIN
VIN
VIN
CCA2
CCA2
CCA1
POL1
22uF 4.7uF 4.7uF
CCA1
POL3
22uF 4.7uF 4.7uF
CCA0
CCA0
INTL4
INTL3
INTL2
+VS
VOUT
VOUT
VOUT
VOUT
VOUT
220uF
47uF
47uF
Vo1
INTL4
INTL3
INTL2
+VS
VOUT
VOUT
VOUT
VOUT
VOUT
220uF
47uF
Vo3
47uF
IM
DELAY
PGND
PGND
PGND
PGND
PGND
PGND
PGND
IM
DELAY
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Figure 18. Complete Schematic of Application with Three Independent Outputs. Intermediate Bus Voltage is from 8V to 14V.
In this application four POL converters are configured to deliver three independent output voltages. POL1 and
POL2 are connected in parallel for increased output current. Output voltages are programmed with the resistors
connected between TRIM and VREF pins of individual converters.
POL1 is configured as a master (IM and INTL0…INTL4 pins are grounded) and all other POL converters are
synchronized to the switching frequency of POL1. Interleave is programmed with pins INTL0…INTL4 to ensure
the lowest input and output noise. POL2 has 180° phase shift, POL 3 and POL4 have phase shifts of 270° and
90° respectively.
All converters are controlled by the common ENABLE signal. Turn-on and turn-off processes of the system are
illustrated by pictures in Figure 8 and Figure 9.
ZD-00697 Rev. 2.1, 11-Oct-2011
www.power-one.com
Page 12 of 18
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